Gil Shacham



Tel: +972-8-9393200

Fax: +972-9-9393223

Address : 12 Hamada st. Rehovot

SatixFy Israel Ltd. is a Fabless developer of ASICs, designed specifically to significantly improve performance in the ground equipment, reduce costs and provide a platform for a wider range of satellite applications.

The ASIC developed by the company, is the heart of the terminal that connects the satellite antenna and customer equipment: personal computer, tablet, Smartphones and others.

The ASIC enables significant price reduction of the satellite terminal equipment, faster Internet connection and a wider range of satellite applications. The company employees have decades of experience in the development of communication systems and VLSI components.

  • Yoel Gat (CEO), was the founder and CEO of Gilat Satellite Networks and founded RaySat which develops satellite communication antenna in motion.
  • Udi Kra (the Program Director), has extensive experience in development of VLSI components.
  • Doron Rainish (CTO), has decades of experience with algorithms and architecture of communication systems.
  • Gil Shacham (VP product), has wide experience in product management from concept through development, to market introduction.

As a part of the consortium, the company cooperates with various companies such as Ceragon, CEVA,  Altair, and also with the Beer Sheva and Bar Ilan Universities.

At the end of the first year of the project, the company is expected to accomplish, within the partnership consortium, the following achievements:

  • Methodology and tools for the production of effective multiplier array, proof of concept and measurement the quality result.
  • Demonstration of software-hardware infrastructure for multi-processor and hardware accelerators.
  • Demonstration of basic environment for high level verification in an architecture combining SOC-DSP algorithms.
  • Completion of the software testing and presentation of the results of the Multi Slice Fast ADC.

After three years of the project, the company is expected to reach the following achievements:

  • Automatic regeneration of system of hardware accelerators based of arithmetic multiplier arrays.
  • An effective system for managing tasks optimized for multi-processor and hardware accelerators in SOC-DSP environment.
  • Completion of a generic SOC platform that can serve a broad family of applications.
  • Completion of a full environment for high level verification architecture and algorithms for SoC-DSP system.
  • Proven ability of ADC multi Slice combining, ensuring the analog interface stay ahead of the technological front