Sharon Kaplan

Homepage: http://www.ezchip.com

Email: Sharon_k@ezchip.com

Tel: +972-4-9596666

EZchip provides a range of powerful and flexible data-path processing solutions that drive networking systems in carrier, cloud, data-center and enterprise networks. High performance and flexibility underscore EZchip’s solutions and enable building high- throughput systems with layer 2-3 switching and routing, layer 4-7 stateful session processing and packet payload inspection, along with fine-grained traffic management. EZchip’s solutions provide the processing engines for a wide array of systems including:

Carrier routers

Network processors for line cards in edge and core routers.

Data center and enterprise appliances

Network processors for accelerating data-path processing, and multi-core processors executing data path and control plane processing, as well as ‘white- box’ network appliances  and intelligent network adapters that incorporate these processors. Typical applications include load balancing, security, deep packet inspection, network monitoring and other appliances that require extensive packet processing.

NFV and SDN

Network processors for accelerating data-path processing, and multi-core processors for executing control and data-path processing, enabling high-performance virtualized networks and virtualized network functions through a variety of form factors including chips in servers and appliances, blades in chassis-based systems, smart TOR (Top Of Rack) switches, ‘white-box’ network appliances, intelligent network adapters and NFV servers.

Enterprise routers and video

Multi-core processors providing complete SOC (System On Chip) solutions for enterprise-class routers for executing the entire networking feature-set as well as video stream encoding and transcoding.

EZchip’s products incorporate extensive software offering and ecosystem enabling customers to leverage standard software development environments and source-level applications library to expedite their own software development and integration processes.

In order to meet the requirements for performance and speed mentioned above, as part

of the HiPer consortium EZchip develop the following 2 technologies:

1. Analyzing performance in HMC which is a new type of RAM technology with very large capacity and bandwidth.

2. Develop Physical design flow for 16/28 nm and perform Process comparison for those 2 most advancing technologies currently in the industry.