A. Instruction flow control
The objective of this task is to develop methods for instruction flow control in DSP processors in order to improve performance by increasing the pipeline length and by improving the utilization of long pipelines. These methods, implemented in hardware, will decrease the number of clock cycles spent waiting as a result of hazards. Our goal is to implement these instruction flow control mechanisms in advanced DSP processors that use the VLIW paradigm to exploit instruction level parallelism available in signal processing applications. The performance improvement in VLIW DSP processors will be demonstrated by DSP benchmark programs.
B. OpenCL in DSP processors
The objective of this task is to develop a multithreaded DSP architecture that supports the OpenCL framework. OpenCL is known as an efficient parallel programming model in heterogeneous platforms that incorporate multicore processors, general purpose GPUs, and FPGAs. The development of OpenCL supporting multithreaded DSPs will enable the use of parallelism available in signal processing applications beyond the capabilities of DSP processors from the current generation. The task includes development of a multicore DSP architecture that is multithreaded at the core level. A VHDL implementation of the architecture will be shown to support the OpenCL framework. Proof-of-concept will be demonstrated by implementing the proposed architecture on an FPGA development board.