ENICS yields fruitful industrial and academic collaboration with more than 30 companies and academic groups around the globe. Currently, the labs employ more than 25 engineers, technical staff and graduate students. The HiPer team includes two Ph.D students, Robert Giterman and Lior Atias and two M.Sc students, Amit Kazimirsky and Miryam Haber
Facilitating 250m2, ENICS labs are equipped with cutting edge EDA tools and IC measurement equipment.
Prof. Fish’s group conducts three projects in the frame of the HiPer consortium:
Embedded memories dominate area, power and cost of modern very large scale integrated systems on chip (VLSI SoCs). Furthermore, due to process variations, it has been challenging to design reliable energy efficient systems. SRAM has been the traditional choice for embedded memory since it provides high-speed read and write operations and static data retention. However, growing memory capacities have led to significant efforts to replace the relatively large SRAM bitcell with a smaller alternative Gain Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While a standard GC-eDRAM inherently provides high-density, low static leakage and 2-ported operation, its limited data retention time (DRT) requires periodic, power-hungry refresh cycles. GC-eDRAM implementations in mature technology nodes, such as 180µm, have been shown to display high DRTs of tens to hundreds of milliseconds. However, while implemented in nanoscaled processes below 65nm, conventional GC-eDRAMs display much lower DRTs of only tens of microseconds. This is a direct consequence of the substantially higher leakage currents which result in a much faster deterioration of the stored levels.
The project, in collaboration with Mellanox and DSPG, includes research and development of a novel GC-eDRAM in 28nm TSMC CMOS technology. The project will examine existing bitcells, as well as eDRAM architectures, recently proposed by the Bar Ilan team. The target of the project is to present a clear advantage of the proposed eDRAM over conventional SRAM memories. We target 30% performance improvement with 20% reduction in area and power.
- High Speed Data Path
Numerous design styles and logic families were previously proposed to enhance design goals. In this project we will analyze, compare and develop both design styles and logic families to best utilize the resources available in the target 28nm process node. In this project we proposed a new logic family and examine its scalability/strengths and weakness in advanced nodes, mainly targeting increased performance though with minimal (or even improved) power consumption.
- Scaling and Process node Comparison
Growing complexity and demand for mobile phones and multimedia applications are pushing chip makers to reach better logic performance. On the other hand, in order to extend battery life, static and dynamic powers have to be reduced. In order to allow a better tradeoff between power-performance-reliability, modern technologies offer many flavors (LP, GP, etc) and many transistors types (LVT, SVT, HVT, etc) within each flavor. For example, a nominal power supply of 0.9V for General Purpose 28nm node achieves the same (or even better) performance than the 28nm Low Power flavor at 1V. On the other hand, it dissipates more power. The question, which technology node and flavor should be used to achieve the best power-performance-reliability tradeoffs for a specific design or system, has become of the most critical questions of design companies.
A SOC or individual ASIC design incorporate many blocks. The task of analyzing a design, exploring it’s weak spots (performance wise) and comparing process nodes is an extremely complex task, time consuming and expensive. Many times this task is not performed well enough, yielding a sub-optimal tradeoff and choosing wrong nodes.
In this research we propose to analyze a design and extract its weak-spots, to analyze both pre-synthesis and post-layout (layout, routing etc.) tradeoffs between nodes. The analysis will be performed for processes, starting from 65nm to 28nm, and in the future, also for 16nm. We plan to analyze each flavor of each technology by an estimation model giving known .libs of the new nodes and to analyze the area-energy-performance-cost trade-offs of a given analyzed benchmark design/architecture without actually performing the whole flow on each path. We will use a model for estimation which then help us to concentrate on the specific flavors of a node (Voltage, VT, tracks etc.).