The proposed research aimed at exploring innovative and high performance power-efficient architectures optimized for specific real time DSP applications using parallel processing and multi-threading. The research will focus on multi-core and vector processing architectures, aiming at exposing both efficient dynamic branch prediction algorithms and new pipeline architectures in multi-core SoC. Additionally, the research will also focus on developing efficient DSP based algorithms and parallel implementation of such algorithms for optimal speed up.
Synopsis of the Current Research:
Real time DSP application parallelism in Multi-core platforms
Video and wireless networking applications widely use DSP cores for their execution. The algorithms are becoming progressively more complex and require increasing computational performance. The trend so far has been to design faster and more complex DSP cores, but the power overhead is becoming too high. It seems that a better performance/power operating point will be achieved by having weaker processing elements that work in parallel. Many DSP systems already employ a few DSP cores which run in parallel. In addition, each core can run multiple threads. In this context, controlling a system with multiple cores and threads introduces the problem of efficient real-time parallel processing implementation. Asymmetry of the cores and threads adds another level of dispatch complexity. This research is aimed at finding an efficient parallelism in the implementation of specific DSP real-time applications using multi and vector processing DSP core platforms and advanced real-time embedded systems. The proposed research aimed at exploring innovative and high performance power-efficient architectures optimized for specific real time DSP applications using parallel processing and multi-threading.