The HiPer Consortium
1. Cut by 50% the time that takes to design and integrate a complex SoC chip.
2. Get a working chip in the first Fab round.
3. Improve the system performance by 30% without compromising on area and power.
To achieve the above goals, the HiPer consortium is conducting cutting edge R&D work in the following technological areas:
1. Establish and implement SoC laboratory in Bar Ilan University that will develop the required infrastructure, tools and knowledge for the rapid integration of SoC in 28nm or smaller geometries.
2. Develop new methods and algorithms for the efficient and rapid data transfer in parallel processing and multicore heterogeneous devices.
3. New and efficient models for the implementation of rapid and cost effective memory models for SoC implementations.
4. Research new models and algorithms to accelerate the performance of multi core, DSP based systems.
5. Research and develop novel methods to conduct process node comparison to match the best fabrication process for a given set of requirements.
6. Develop methods and tools for an early evaluation of system performance.